The present invention relates to a semiconductor design technology, and in particular, to a row path design of a semiconductor memory device. More particularly, the present invention relates to a negative word line driving technology.
A semiconductor memory device may be configured by a group of memory cells, which form basic units. A large number of memory cells are arrayed in a matrix form. A memory cell of a dynamic random access memory (DRAM), formed as a representative semiconductor memory device, includes one NMOS transistor and one capacitor.
FIG. 1 is a circuit diagram illustrating a configuration of a conventional DRAM cell.
Referring to FIG. 1, an NMOS transistor T of the DRAM cell has a gate connected to a word line WL, and a source connected to a bit line BL. A capacitor C of the DRAM cell has a storage node connected to a drain of the NMOS transistor T, and a plate node connected to a cell plate voltage terminal.
The word line WL is a signal line that is selected by a row address to select and activate a corresponding memory cell. When a certain word line WL is selected, a high voltage level (VPP) is applied to the selected word line WL so that a cell transistor T connected to the word line WL is turned on. A primary data transfer occurs through charge sharing between a storage node of a capacitor C and a bit line that is a signal line through which data is inputted or outputted. This is a basic active operation of the DRAM.
In a precharge operation of the DRAM, the word line WL selected in the active operation changes to a ground voltage level (VSS). Thus, the cell transistor T is turned off and data is stored in the storage node of the capacitor C.
Meanwhile, since the memory cell of the DRAM has a leakage current even if it is unselected, the stored data may be lost after elapse of a certain time. To prevent the loss of data, it is necessary to perform a refresh operation to amplify and restore data of the storage node at predetermined time intervals.
A characteristic time taken in physically losing data at the storage node is called a refresh characteristic. As the integration degree of a DRAM fabrication process is improved, the spacing between a memory cell and its adjacent part is gradually narrowed, causing increase of a leakage current at a storage node. In addition, as a capacitance of a storage node itself becomes smaller, the refresh characteristic is further degraded.
Meanwhile, a method of increasing a threshold voltage of a cell transistor may be used for reducing a leakage current at the cell transistor. However, if the threshold voltage of the cell transistor is increased, time taken to store data in the storage node is increased.
A negative word line scheme may improve refresh characteristic, without degrading characteristic of time taken to store data in a storage node, because a leakage current is controlled using a gate-source voltage (Vgs) relation of a cell transistor, without increasing its threshold voltage, by maintaining a potential of a word line to a negative potential lower than an existing ground voltage level (VSS) in a precharge state where a word line is unselected.
However, the negative word line scheme has a disadvantage in that current consumption increases according to increase of a potential variation width (swing width). That is, a selected word line is at an external high voltage level (VPP), and an unselected word line is at a negative word line voltage level (VBBW) lower than a ground voltage level (VSS). Hence, the potential variation width of the word line is increased compared with the case the negative word line scheme is not used. The current consumption increases. Also, an internal voltage circuit generating the high voltage and the negative word line voltage must manage a larger amount of current.
If a bit line and a word line are shorted, current consumption is increased by the application of the negative word line scheme.
Meanwhile, in the case of a transistor having a low threshold voltage, such as FinFET, it has been necessary to apply the negative word line scheme on an entire cell array. However, in the case of a transistor having a recessed channel structure, it has not been always necessary to apply the negative word line scheme on the entire cells because a threshold voltage is not lowered.
In such a structure, if the negative word line scheme is applied on the entire cells, a channel doping of the entire cells can be lowered and therefore a channel threshold voltage can be lowered. This means that the transistor has an appropriate current drivability even though the high voltage used as a word line driving voltage is lowered.
In this case, however, a neighbor gate effect that a channel voltage is fluctuated due to neighbor word lines may worsen. That is, if a selected word line is activated to a high voltage level, a channel area controlled by a neighbor word line sharing an active area with the selected word line experiences a large voltage rise because a channel doping is in a very low state by the application of the negative word line scheme. This degrades an off characteristic of the corresponding cell, resulting in increase of a leakage current.
Compared with a transistor having a planar channel structure, a transistor with a recessed channel structure may be affected more severely because a channel of a neighbor cell faces a word line passing aside. Moreover, compared with the transistor having the recessed channel structure, a transistor having a saddle gate structure may severely affect a channel of a neighbor cell.
Meanwhile, as the technology is advanced, the spacing between word lines gets narrower. In this case, a neighbor gate effect is becoming a more significant concern.